Exaplain about your project and entire data path of RISC V architecture
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
A design has 2 types of cmds - read and write packets. You need to send 10 back to back cmds through a sequence in such a way that after a write cmd was previously sent, you cannot immediately send a read cmd. However, the 1st cmd sent can be write cmd.
Name and describe the differences between SystemVerilog forks.
how do you verify 32 bit adder
Difference between latch and flipflop
1) interrupt mask register (10 bits) - Each bit corresponds to 1 interrupt interrupt log register (10 bits ) - Each bit corresponds to 1 interrupt Interrupt mask register masks the interrupt from reaching the output pin i.e , the output pin shows 0 although theres an interrupt Interrupt log register logs the presence of interrupt , but the moment you do a read , the interrupt log reg bit goes to 0 . Best strategy to verify ?
What is deep copy and shallow copy in System Verilog? Can you tell about sequencer in UVM and what is the use of it? What is virtual interface and why it is used? Gave a Constraint and asked what will be the randomised values. Asked to write an assertion for a given scenario Asked to write a constraint such that it will generate even and odd numbers in sequence.
Code for fsm,digital electronics and sta
Draw an AND gate using transistors.
What are the limitations of current design methodologies?
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