asked about uvm and system verilog.few questions about sv constraints
Verification Engineer Interview Questions
3,720 verification engineer interview questions shared by candidates
Generate a clock divider using or gate
Technical questions: the same as LeetCode questions - Merge Sorted Array
Traversal of a binary tree to find given value
write a system verilog code to merge two sorted array and create a merged sorted array
Mainly riddles, about gates and other components
System Verilog and Formal Verification
Draw a FSM sequence detector
What is your greatest weakness?
Writing MIPS assembly code with hazards recursive function program
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