technical questions including cache design, carry adder, verilog un/signed adder, fifo synchronous pointer
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
1. Given a set of specifications for register elements , how do we compute the maximum frequency of operation? 2. What are the different types of constraints used in design , when and how are they specified?
About counter and asked to design them
What's the 2 principle of Cache.
State Machine design , SRAM basics
how to you put synchronous and asynchronous reset in your code? what is the pros and cons of both situation.
how do you perform floating point addition in hardware?
If the incoming data to the FIFO is 1Mhz and outgoing data is at 1Khz and the data is 32 bits wide, what would be the depth of the FIFO?
How is organized a CPU?
Questions covered computer architecture, timing problems, power analysis, and design problems
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