Describe clock domain crossing techniques
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
Self intro, basic definations in CTS and STA, low power design methodologies, local vs global skew, problems on sta
Async fifo design and SDC contraints for it. Pulse synchronizer cross clock domains.
Lots of questions on OoO processor and Caches Learn more than what is given in your coursework
ASIC design processes, techniques, design processes
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
Based in UVM and System verilog and project related questions
Asked me to draw a boolean expression using only NAND gates.
latch vs FF
Basics of digital K map based questions Verilog programing some logical ability questions
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