Explain and design a two level branch predictor
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
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FIFO fundamentals (synchronous) and depth calculation, arbiter fundamentals (fixed priority, round robin, weighted), experience with cache, how to optimize a given logic path for timing assuming area is no concern, my ASIC design experience (timing closure, microarchitecture, block explanations).
Hiring managers asked about project details and tools. He was expected digital design solutions and CDC related topics. Lint and Lowpower design questions asked and given FIFO calculations. Current company job roles and responsibilities and challenges in current project
synchronization of multiple control signals FIFO Depth calculation
Design a NAND2 gate using CMOS transistors.
sync vs asyc rst
Can you sell this product? I answered that I could sell anything if I knew something about it. Supply and demand.
Questions were standard interview question on synthesis and lint
What can you offer to this company
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