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Simple but a very interesting question. I was given a Verilog code of about 60 lines and I was asked on whiteboard to explain how that RTL will get synthesized to, as in depending upon priorities what muxes & how the counter will be synthesized.
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DFT Lead Engineer

Interviewed at Avago Technologies

3.1
May 15, 2013

Simple but a very interesting question. I was given a Verilog code of about 60 lines and I was asked on whiteboard to explain how that RTL will get synthesized to, as in depending upon priorities what muxes & how the counter will be synthesized.

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