How is organized a CPU?
Design Rtl Interview Questions
274 design rtl interview questions shared by candidates
What's the 2 principle of Cache.
State Machine design , SRAM basics
Questions covered computer architecture, timing problems, power analysis, and design problems
I report only the technical questions: - how the asynchronous reset can cause issues in a synchornus system - Pipelining (open question) -definition of setup time and hold time -Techniques to reduce power consumption (open question)
Caches
mealy and moore state diagram sequence generator, question regarding course project
Fixed priority arbiter, Arbiters(4 clients 2 with fixed priority and 2 with round robin), FSM(sequence detector, Lift Controller), How to change reset value of register during an ECO
technical questions including cache design, carry adder, verilog un/signed adder, fifo synchronous pointer
1. Given a set of specifications for register elements , how do we compute the maximum frequency of operation? 2. What are the different types of constraints used in design , when and how are they specified?
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