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Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
What motivates me from day to day
They shared the specific scenario and asked how would I solve it. So they are checking your problem-solving skills.
Technical questions related to digital design, based on projects from your CV and verification languages, methodologies. Questions were basic ones and there were a few scenario based questions too.
asked in system verilog and UVM
Technical questions related to job role
What is your expected salary?
Verification plan for a given scenario, what are the possible ways we can verify.
What is the difference between calloc and malloc?
They asked: blocking, nonblocking statement, asked to write a code for a given circuit, then they asked about asynchronous, synchronous reset, how and where they are applied. In second round, they asked question based on processor design, FIFO, STA.
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