How would you test a component that splits the memory for 8 different data streams
Verification Engineer Interview Questions
3,715 verification engineer interview questions shared by candidates
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
Not Applicable and confidential as per norms
C++ encapsulation, inheritance and polymorphism
Nothing was unexpected, very minimal behavioral questions. All the technical questions are regarding to computer architecture subjects.
ask the concept of virtual function, pure function in c++. Ask previous verification experience. An question about how to write a c program to judge whether a machine is big-endian or little-endian
Given read and write freq, how to calculate FIFO depth?
First Phone interview Computer Architecture stuff: OOO, memory dependencies, Piplelining, Fetch stage, Branch Prediction System Verilog: coverage and assertion writing Digital Logic: Implement AND and OR using 2:1 mux Asked to rate myself in C++, System Verilog Second Phone Interview: Similar Comp Architecture questions C program to sort array. Binary search vs Linear Search. Time complexity.
No difficult question. Only job shadowing did not really mean job shadowing!
questions about OVM process
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