Mostly technical scenario based.
Verification Engineer Interview Questions
3,721 verification engineer interview questions shared by candidates
Talk about the project that I did, which is designing a single-cycle processor
Basic question related to verilog, SV, digital, UVM, project done
What is flipflop latch logical quese
Projects
constraints
Digital electronics basics and verilog basics
Basic questions on Verilog Combinational and sequential coding differences, Coding a state machine, Timing problems Was asked to explain my projects
Write a simple uvm sequence template and explain each line.
Why do we use n-mos over p-mos? What are the different types of diodes? Functioning of BJT, J-FET, CMOS technology.
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