Advantages of UVM verification over SV
Verification Engineer Interview Questions
3,723 verification engineer interview questions shared by candidates
What are your strengths and weaknesses?
how to communicate the data through different time domain.
C++ questions
Correction in the circuit drawn.
None
FSM problem. i had to write the state machime to find if the number was divisible by 3 or not. sequence detector for divisible by 3 numbers in cummulative manner.
Nothing special, asked about the work I had done so far.
vmm is used extensively and people over there dont know ovm or plane system verilog is better thatn vmm
Analog Questions
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