digital, verilog, system verilog
Verification Engineer Interview Questions
3,723 verification engineer interview questions shared by candidates
basics of Digital, SV UVM, coverage , assertions,
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
show how code coverage and function coverage works. explain with code
APB and AXI protocol explation with all signals.
About Electronic basics and Communcation basics
How would you handle an irate customer? What process would you follow to resolve the issue?
Write verilog code for any flipflop. variations were also asked.
design logic gates few questions on Verilog coding
completely based on system verilog and digital design concepts
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