Based in UVM and System verilog and project related questions
Verification Engineer Interview Questions
3,722 verification engineer interview questions shared by candidates
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
paging, hypervisior,
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
Why do we need virtual memory and whats the advantage of having it?
Do not want to give it away but learn computer architecture well
SV, V, UVM, Problem solving, Advanced formal verification based questions, experience based questions
Questions on computer architecture, bitwise C, exercise on HDL/C/pseudocode for an FSM, logical circuits There was an emphasis on describing my thought process for my solutions rather than their actual results.
Most of the things were on ARM architecture, AMBA protocols, SV and UVM, Design concepts and Analytical skills
Microprocessor Interrupts C programming ARM architecture Amba
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