If your constraint block includes values like 0, 1, 4, and 300 to 400, how would you handle that in coverage?
Senior Asic Verification Engineer Interview Questions
274 senior asic verification engineer interview questions shared by candidates
Given a diagram, how would you verify a design/check output data. Computer arch basics and design questions
functional, code coverage ,priority encoder explanation, SV
Calculate bandwidth for 16 bit data bus, data rate: 50 MHz and only 25% of time.
I had a phone screen - basic SV and UVM multiple choice questions. Second round - OOPs concepts, some verification concepts (types of coverage, stimulus).
System verilog, UVM scoreboard/monitor coding
1. Some simple random stimulus with specified constraints
Read after write sequence implementation
Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Linked list, Bit manipulation, Pipeline
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