FIFO depth
Rtl Design Interview Questions
274 rtl design interview questions shared by candidates
nothing as such..everything was from what i had studied in BS and MS
Low power implementation - UPF Level shifters, isolation cells, retention cells, clock gating, PoR sequence etc.
I could not reveal the questions
The interview began with fundamentals like race conditions, reset types (synchronous vs. asynchronous), and their advantages. I was then asked to write RTL code for a basic flow, with the interviewer gradually increasing complexity by adding registers and FIFO elements. In the final part, I explained my projects in detail, focusing on my contributions, design decisions, and verification approach.
synchronization of multiple control signals FIFO Depth calculation
Design a NAND2 gate using CMOS transistors.
sync vs asyc rst
Can you sell this product? I answered that I could sell anything if I knew something about it. Supply and demand.
Questions were standard interview question on synthesis and lint
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