Lots of questions on OoO processor and Caches Learn more than what is given in your coursework
Rtl Design Interview Questions
274 rtl design interview questions shared by candidates
ASIC design processes, techniques, design processes
Self intro, basic definations in CTS and STA, low power design methodologies, local vs global skew, problems on sta
Describe clock domain crossing techniques
Async fifo design and SDC contraints for it. Pulse synchronizer cross clock domains.
About counter and asked to design them
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
Based in UVM and System verilog and project related questions
Asked me to draw a boolean expression using only NAND gates.
latch vs FF
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