Explain flow from RTL TO GDS11 in a design project i have done, how signal integrity affects the hold and setup times.
Physical Design Engineer Interview Questions
3,254 physical design engineer interview questions shared by candidates
He asked me about my design project which I did during my Masters, Timing analysis, Flipflops, PD Flow
STA, CTS, Floor planning, Logic Circuits, PNR 1. What is OCV and derate factors 2. Calculation of setup and hold slack (Given values, Thold, Tsetup, Tlogic, derate factors) 3. How to reduce setup violations and hold violations? 4. Difference between H-tree and Mesh? 5. Techniques to reduce clock power? 6. Low power design techniques 7. What is Multi Bit FF? 8. Draw basic logic gates (And) using NOR (NAND) gates? 9. Crosstalk glitches? 10. Placement of macros questions 11. How to calculate channel spacing between macros/ 12. SRAM design questions 13. Physical only cells- Tap cells, Tie cells use and where do we place them 14. How Delay of a net/cell changes with VDD/ 15. Capacitance and Resistance of wire effects on delay and how to reduce it? 16. How to reduce static, Dynamic, short -circuit power? 17. Where to use LVT, HVT cells? 18. Difference between local skew and global skew? 19. Verilog Coding question- Synchronous and Asynchronous DFF 20. What is the use of End cap cells and Decap cells?
mathematics
6T SRAM working
how an inverter behaves when input goes from 0 to 1
Questions mainly based on resume and a few STA questions, questions based on CMOS.
What do you know about physical design in vlsi?
Design an NOR gate using a Multiplexer
What is your current pay ?
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