Transistor level details from college level courses.
Physical Design Engineer Interview Questions
3,254 physical design engineer interview questions shared by candidates
tell me about your block
Timing analysis, digital logic design, transistor sizing and parasitics.
Setup hold time dependency factors in a flip flop
Setup and hold constraints for negative and positive clock skew
explain synthesis process, and problem.
Draw CMOS circuit of some gates. Write script to identify missing random number.
Experience, areas of expertise, certifications
Body effect CMOS working
What is a scenario where you had conflict?
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