-MOS operating regions -PLL locking mechanisms -impedance of cross coupled diff pair
Ic Engineer Interview Questions
585 ic engineer interview questions shared by candidates
standard cell libraries and how they get used by synthesis tools
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How do you create a voltage higher than supply voltage in your circuit?
Tell us an occasion, where you had to write some behavioral code in Verilog.
Questions on On chip variation and what causes them. Was asked how I'd model them. i mentioned timing derates -which are a very old technique. Was asked if i worked with AOCV models. Was asked few questions on clock jitter
Design a synch FIFO. Was asked a simplified version. Was asked to assume depth of FIFO was 4 and width was 32. He was just looking for how and when I'd update the memory buffer and the control logic for the free and avail Was given a verilog module and asked to figure out what it was doing. Noticed that it was a round robin-ish arbiter. Later was asked if there was any case where starvation (live lock) was possible. It became clear as I was working thru the waveforms there was a specific case where the arbiter can starve any of the requests. Then I was asked to fix the code. Also I was asked how would we catch issue like this. I mentioned that Formal Prop Verif tools are the best vehicles to find bugs on such designs
Describe your current role. Send a pulse from one clock to another clock. How to send data from one clock domain to another. Minimum sizing of an async FIFO
project on which i worked
mostly questions from resume and typical new grad questions
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