The first one is a FSM for a vendor machine and the second one is about CPU pipeline, third one is the how cap and res will be for a long wire then we talked about the job and the company, the gay was nice and tried to help me with the problem I had difficulty, but I still miss one possible situation for the FSM and missed one step for the CPU pipeline. After about half a month I was told no further round, so sad.
Describe a CMOS Inverter.
Basic system verilog questions, scoreboard, semaphores, mailboxes, etc
How do you handle traffic between 2 units using a FIFO?
Questions from Testing and Verification on topics like BIST, MISR
Cache, Coherency, Virtual Memory, FSM for Overlapping and non-overlapping sequence detectors. Given the waveforms fora set of 3 signals, deduce the final circuit, find the bug in the system where the system specs are given with the output waveforms, System Verilog and OVM based questions as i had mentioned it on my Resume (through internship).
Some basic verilog and C++ questions.
The reason why you leave your last job
They asked me about my experience with FPGA
Types of leakage in CMOS.
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