design a module using any HDL that recives pulses and the goal is to detect 10 pulses within 100 cycles, the interesting part is the ability to detect 10 ulses from the moment we get each pulse. for example: lets say we get a pulse start counting the 100 cycles, if we reach 10 pulses before the time ends then start counting from the time we received the second pulse until the eleventh and so on.
Introduce yourself please .what is carrier goal
About ethernet communication and timing system.
Basic questions on Analog and Digital
HR: What do you know about Maxeler? What do you think about working in a small company? Tech: Detail the FPGA structure. Explain the difference between polymorphism and function overload. If you have to build a compiler, what language would you use? Other questions about computer arithmetic.
Fourier transform
basic questions about FPGA
implement a box that have an input data (1 bit) that has pulses of 1 clock width (clk_in) and one output data that has a different clock rate (clk_out: faster/smaller), and the data should go out for only one clock pulse (in clk_out). what are the limitations in rate of such box. note that you can use only FPGA existing components
A question on FIFO depth and Constrained Random Verification
Embedded C related questions
Viewing 581 - 590 interview questions