Name the testbench components of this diagram. Is a start(seq) blocking or non-blocking?
Fpga Design Engineer Interview Questions
681 fpga design engineer interview questions shared by candidates
Previous projects, Fundamnetals of HDL and FPGA and tools. DO-254 and reliability engineering.
How do you do clock domain crossing of one and multi bit signals?
Can you write a Verilog module for a parameterized counter and explain how you would verify it?
Write a sequence detector FSM in verilog
Shift registers for flipping certain incoming bits
What was a past project you had in FPGA and what made it challenging etc
Questions on AES, block ciphers. Questions on synthesis, placement flow in FPGA. Difficulties faced in FPGA projects.
What is Sta cdc metastability
No questions since they did not show up.
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