Technical questions on software, such as object oriented programming. There were also questions on computer architecture testing my understanding of concepts such as pipelining.
Design Verification Engineer Interview Questions
3,722 design verification engineer interview questions shared by candidates
Walk through the CV and deep dive the previous project technical details. Many general questions related to verification methodology.
Find a bug in Fifo verilog code
C++ Questions, memory allocation
What Is UVM? What Is the Advantage Of UVM?
What is your expected salary?
Stack, heap, computer architecture related questions. Cache coherence.
Verification plan for a given scenario, what are the possible ways we can verify.
What is the difference between calloc and malloc?
They asked: blocking, nonblocking statement, asked to write a code for a given circuit, then they asked about asynchronous, synchronous reset, how and where they are applied. In second round, they asked question based on processor design, FIFO, STA.
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