Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Asic Verification Engineer Interview Questions
274 asic verification engineer interview questions shared by candidates
Read after write sequence implementation
round robin algorithm, scheduling? state diagram?
Black box CRC circuit checking...
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
Why OOPs is important
- about SV, FIFO design, arbiter design
Then asks questions in SV & UVM starting from basic concepts to transaction level modelling & even asks you to develop a UVC for a protocol.
My projects which was relevant to job role
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