> Asked questions related to fifo. Was not a direct question , they have explained a particular scenario with combination of fifos along with pictures , and the question will be crystal clear. > Multiple questions were there based on basic test bench architecture and how to build a test bench with a given design as example
if the inverter's input is connect to its output. how the output voltage curve should be like
In technical interview, they asked: (1) about yourself (2) where did you hear the company (3) explain fundamentals regarding electronic elements e.g. diode, bjt, fet, opamp, capacitors (4) college thesis (5) what should they expect from you
Verilog tasks and functions, FSM Design, FIFO Depth, some system verilog questions.
blocking and non-blocking
Where do you see yourself in five years.
What should be the size if it is receiving data and also loosing some packets ?
Where are gray counters used?
Design xor2 gate using only nand2 gates
Design xor2 gate using two 2-input muxes, inputs A and B, power and ground.
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