Tell me about a class you like?
Asic Design Verification Engineer Interview Questions
274 asic design verification engineer interview questions shared by candidates
what do u know about virtual pages
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Constraint randomization based question linking to AXI and memory filling
Node insertion in linked list. Fibonacci series function, hardware to generate Fibonacci series, prime number generation hardware , STA concepts, clock domain crossing, use of synchronizes, skew and setup hold time violation.
Explain past work experience and Project details.
pass by value, pass by ref, function in c for fibonacci, pattern detector fsm, pipeline hazard
Scripting questions on 2D hashes and asked for coding in perl/python. Basic questions on STA
I don't remember the question clearly but something that had to do with implementing some methods in a (UVM-like) Scoreboard class.
Viewing 211 - 220 interview questions
See Interview Questions for Similar Jobs
Fpga Development EngineerAsic Verification EngineerHardware Asic Design EngineerFpga Design EngineerVerification EngineerVlsi EngineerDesign Verification EngineerVlsi Design EngineerFpga DeveloperSenior Asic Fpga Design EngineerFpga EngineerSenior Vlsi Design EngineerSenior Dft EngineerSenior Asic Design EngineerDesign VerificationCpu Design EngineerSenior Fpga Design EngineerDigital Asic Design Engineer