Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
Where do you see yourself in 5 years?
Asked questions about clock domain crossing , low power techniques
What are setup time and hold time?
Why OOPs is important
Static Timing Analysis questions.
Explain the last project
How does Cadence Encounter solve setup time violations before CTS
ASIC flow, setup/hold, fix violation
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