Basic electronics question - 2:1 Mux, truthtable, DFF, FPGA design flow
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
What is multicycle path, what is CDC?
They concentrate more on your technical knowledge over Architectural Design and Problems you tackle. As well as a Ciding for Automation
One hot encoding, FSM divide by 3, Verilog coding.
Read after write sequence implementation
General questions about caches / memory systems.
write assertions to verify the condition.
They asked about click domain crossing what do I know?
Standard digital design questions: 1. FSM 2. Multiplier design/questions 3. sync vs async reset
Cache coherency, mapping techniques, metastability, cdc, synchronizers,
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