design sensor with minimal logic block
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
Write a Fibonacci number generator in Verilog, output a number in each cycle.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Digital Design basics
explain about cache
What is a fpga and what is a lookup table?
ok. fifo..design n implementation.and other designing questions
The interview was straight forward and aveage
where do you see yourself in 5 years
Explain the working of a FIFO.
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