I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Asic Design Engineer Interview Questions
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All questions were related to my previous experience, testing methodology, and problem solving skills. They also asked some basic oo concepts
Sequence detector with FSM Synchronization Cache
Design a CAM.
Asynchronous FIFOs. These guys love them.
Frequency divider
Setup hold time calculation
CMOS characteristics?
what do u know about virtual pages
pass by value, pass by ref, function in c for fibonacci, pattern detector fsm, pipeline hazard
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