Basic Questions on blocking/non-blocking assignments, STA, resets etc. Questions on system design, congestion solving problem.
Asic Design Engineer Interview Questions
1,319 asic design engineer interview questions shared by candidates
Systemverilog and UVM questions
Based on the critical, find the max frequency of operation (based on the combi, flop delays, flop setup and clock skew).
Question on power optimization technique beyond what the tools have options, basically looking for some innovative way of power optimization.
Coding to parse a netlist
What challenging project you worked upon?
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
What is MOSFET, EDA etc.
ok. fifo..design n implementation.and other designing questions
What is a fpga and what is a lookup table?
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