Missions

Menta is looking a STA Software Engineer to join our team and contribute to the development and optimization of our Static Timing Analysis (STA) tools. The ideal candidate will have a strong background in either hardware design or software development, with an eagerness to work on complex timing analysis algorithms and improve EDA tool performance. This position offers the opportunity to work on both software development and hardware design concepts, leveraging your understanding of STA principles and translating them into efficient, scalable software solutions.

Responsabilities

• Develop and optimize Static Timing Analysis (STA) algorithms for EDA tools.
• Collaborate closely with hardware engineers to translate STA concepts into software implementations or with software engineers to enhance tool performance.
• Design, implement, and maintain timing analysis features, focusing on optimization and efficiency.
• Work on the integration of timing closure tools within the overall design flow.
• Contribute to the design of user interfaces (GUI) to visualize timing results and analysis for end-users.
• Write clear, maintainable, and efficient code while adhering to best software engineering practices
• Conduct performance optimization and handle scalability challenges in large-scale designs
• Collaborate with cross-functional teams to continuously improve and update STA algorithms

Skills & Experience

Desired skills and experience

• MS or a PhD in Computer Science, Electronics, Mathematics or related discipline
• 5+ years of experience in developing applications in C++
• 2+ years of experience in QT
• For Hardware Engineers transitioning to Software: Strong background in hardware design (FPGA/ASIC) with an interest in software development (C++, Python).
• For Software Engineers with STA focus: Solid experience in C++ programming, algorithm design, and understanding of timing analysis principles.
• Experience with Static Timing Analysis (STA) concepts, tools, and workflows.
• Familiarity with timing analysis tools and methodologies (e.g., timing path analysis, constraint-driven design).
• Proficiency in C++, and knowledge of Python or other scripting languages is a plus.
• Knowledge of EDA tools (e.g., Cadence, Synopsys, or similar) and ASIC/FPGA design flows.
• Familiarity with version control systems (e.g., Git or SVN) and a collaborative development environment.
• Excellent problem-solving skills, attention to detail, and the ability to work in a fast-paced environment.
• Good written and spoken English is mandatory

Environment